1. Field of the Invention
The present invention relates to a semiconductor integrated circuit in which at least one of power supply terminals or ground terminals connected on a power supply path of an output circuit for driving a signal to the outside of the integrated circuit is installed independently of a power supply path of an internal circuit responsible mainly for logic operations. More particularly, this invention is concerned with the integrated circuit in which the cost of a semiconductor integrated circuit can be reduced by decreasing the number of terminals associated with signals which are employed in a special state as a test or the like or used for newly added functions.
2. Description of the Related Art
In recent years, semiconductor integrated circuits have had the tendency toward higher integration and higher multifunctionality. Labor and cost of a test for checking if a manufactured integrated circuit operates normally are increasing accordingly. For carrying out such a test on a semiconductor integrated circuit, special signals for the test are employed in general. For example, a terminal for inputting a mode change signal for changing an operation mode to a test mode, and a terminal used to input a test signal for some test from the outside of the integrated circuit or a terminal used to output a signal from the integrated circuit under a test to outside are needed.
These terminals employed in the test become unnecessary for actual use (normal operation mode) of the integrated circuit after completion of the test that is an original object of the terminals. Moreover, if the number of terminals unnecessary in the normal operation mode is large, various problems occur. For example, it becomes hard to design a package compactly.
The present invention does not restrict an object of test on a semiconductor integrated circuit to any specific test. Moreover, the test is not limited to literally a test on a semiconductor integrated circuit but may be concerned with a special state analogous to a testing state. A general test requires terminals for inputting and outputting some test signals or a terminal for inputting or outputting a test signal bidirectionally.
For example, there is a standby current measurement that is one testing method for a semiconductor integrated circuit such as an LSI. This standby current measurement is such that a logical state to be input to a semiconductor integrated circuit that is an object of the measurement, a logical state to be output from it, or a logical state of the inside of the integrated circuit is set to a steady-state, and a supply current in the steady state is measured. In a complementary metal oxide semiconductor (CMOS) type integrated circuit, a leakage current flowing when a MOS transistor included is OFF can be measured. Through the measurement, the presence or absence of a MOS transistor deteriorated or failed can be judged.
Talking of a defect of a semiconductor integrated circuit, for example, if the circuit is cleaned insufficiently in the course of manufacturing or a foreign substance adheres to the circuit, the operational characteristic of the circuit may be degraded or the circuit may become completely defective some days later. In this case, the standby current measurement can be adopted for detecting a leakage current and thus judging if the circuit is defective.
The standby current measurement may be referred to as an IDDQ test or steady-state current IDDQ measurement test. An evaluation testing pattern adopted for this kind of test is selected from among, for example, numerous testing patterns designed for functional tests by users. However, if a current larger than a leakage current flows for some reason, for example, a current flows into a pull-up resistor as described later, some of the evaluation testing patterns are ineffective in detecting the leakage current hidden behind the large current. When a pull-down resistor is employed, if a current flows into the pull-down resistor, the leakage current cannot be detected successfully. A testing pattern causing a large current to flow or a circuit pattern causing the operation of a circuit to become unstable cannot be adopted.
For a circuit having a pull-up resistor, the standby current measurement must be carried out with the logical state of a pulled-up portion of the circuit set to a high-level state. For a circuit having a pull-down resistor, the standby current measurement must be carried out with the logical state of a pulled-down portion of the circuit set to a low-level state. It is therefore very difficult to produce a testing pattern to be used for the standby current measurement.
For reliably finding out the presence of a deteriorating or failing transistor or the like through standby current measurement, a static current should preferably be able to be measured with each node set high or low. However, when each node is set high or low, if a current flows into a pull-up resistor as mentioned above, the static current cannot be measured.
Japanese Patent Publication No. Hei 4-152714 has disclosed an art in which a control signal terminal is included to give control signal so that a pull-up resistor or a pull-down resistor is disconnected at the time of standby current measurement to prevent a current from flowing into the pull-up resistor or pull-down resistor during the standby current measurement. According to this Japanese Patent Publication, for example, a p-channel MOS transistor or an n-channel MOS transistor to be turned ON or OFF in response to a signal applied to the control signal terminal is used to disconnect the pull-up resistor or pull-down resistor at the time of the standby current measurement. Since no current flows into the pull-up resistor or the pull-down resistor during the standby current measurement, any of testing patterns can be selected more freely.
By contrast, a method referred to a scan path method is adopted for simplifying a test on a semiconductor integrated circuit such as an LSI. The scan path method is such that all flip-flops in a circuit are isolated from normal circuit connections at the time of testing, and used as one long shift registor. In this method, an access to each flip-flop during testing is completed as one shift registor.
For example, all flip-flops are operated as one shift register, and a desired testing pattern is input serially. For reading the logical states of the flip-flops, all the flip-flops are operated as one shift register, and the logical states shift successively.
In general, a logic circuit can be classified into a sequential circuit such as a flip-flop or counter and a combinational circuit such as a gate. In the scan path testing method, a logic circuit can be tested by dividing it into a part of sequential circuit and a part of combinational circuit, and then subjected to a test.
By contrast, a known method of testing a semiconductor integrated circuit such as an LSI includes a method using a so-called boundary scan register.
This method is such that boundary scan registers are connected in advance to an input or output terminal or the inside of a logic circuit to be tested, such as, a user circuit. In setting the logical state of the input or output terminal of the logic circuit to be tested, or in reading the logical state of it, access is carried out via the boundary scan registers.
A general boundary scan register is composed mainly of a flip-flop and multiplexer. For setting a logical state, the multiplexers in respective boundary scan registers are switched so that the numerous boundary scan registers constitute one long shift register. A serial data pattern is input while being successively shifted from one of the boundary scan registers constituting the shift register to another, whereby the logical states of the respective boundary scan registers can be set.
For reading the logical states of the boundary scan registers, the multiplexers in the boundary scan registers are switched so that the numerous boundary scan registers constitute one long shift register. Data is successively shifted from one of the boundary scan registers constituting the shift register to another, whereby the logical states of the boundary scan registers are read successively to the outside of the semiconductor integrated circuit.
The standby current measurement method, the scan path method, and the testing method using boundary scan registers have been described as methods of testing a integrated circuit such as an LSI. The present invention is not limited to these methods. Almost all methods of testing a integrated circuit including these methods use special signals for testing.
For example, in the scan path method, as mentioned above, at least a signal for changing all flip-flops in a circuit to be tested to a long shift register is needed. The testing method using boundary scan registers requires a signal for switching multiplexers in boundary scan registers. In the standby current measurement, generally, a signal dedicated to testing is needed as described in the Japanese Patent Publication No. Hei 4-152714.
Japanese Patent Publication No. Hei 6-77330 has disclosed an art in which a circuit shown in FIG. 10 is used to decrease the number of signal terminals employed in a test on a semiconductor integrated circuit.
According to the Japanese Patent Publication No. 6-77330, included are a mode change terminal .PHI. for changing an operation mode in which a circuit performs a given operation to a test mode in which the circuit performs a testing operation, and a power supply terminal VDD and a ground terminal GND to which given power supply voltages are applied. In addition to these terminal, a power supply/testing terminal 16 (VDD/TIN in FIG. 10 connected in parallel with a power supply terminal VDD) is included. In the operation mode, the given power supply voltage is applied to the power supply/testing terminal 16 in parallel with the power supply terminal or the ground terminal. In the test mode, the power supply/testing terminal 16 is disconnected from the power supply terminal or the ground terminal by a switching circuit 22 so that a testing signal can be input or output through the terminal.
In FIG. 10, there are shown a power line 24, a protective circuit 20 composed of two diodes, and a gate circuit 26 for supplying a signal to an internal circuit in the test mode.
In the Japanese Patent Publication No. Hei 6-77330, the switching circuit 22 (test selection switch) is placed between the power line 24 and power supply/testing terminal 16 in order to use the terminal 16 as a testing input terminal in the test mode. By contrast, in the normal operation mode, the terminal 16 is used as to a power line 24 for supplying power. The terminal employed in the special state in which a test or the like is carried out is utilized for supplying power in the normal operation mode. As a result, the number of terminals that become unnecessary in the normal operation mode can be decreased.
However, in the normal operation mode, although the terminal 16 is used as a terminal for supplying power, the switching circuit 22 is inserted on a power supply path. Even when the switching circuit 22 is ON, some ON-state resistance exists in the switching circuit 22. This causes a problem that the regulation in power supply deteriorates due to a voltage drop. The deterioration results in some performance degradation of the integrated circuit.